Surfer Memory and Wide Array Support
Contributor: Kutikuppala Deekshita
This proposal focuses on enhancing the Surfer waveform viewer by adding support for memory and wide array visualization. Current waveform views are...
Other
Free and Open Source Silicon Foundation
Working together for Free and Open Source Silicon
Technologies
CompilerRISC-VverilogvhdlWeb
Topics
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- Total projects
- 64
- Years participating
- 11
- Most recent
- 2026
Participation history
Historical projects
Using AI to Improve Open-Source IP
Contributor: Muhammad Rayyan Khan
Millions of lines of open-source Verilog exist but remain verbose and hard to maintain. TL-Verilog offers a cleaner abstraction, but almost none of...
RISC-Vverilog
Robust Implementation and Verification of the RISC-V Svadu Extension for Ariane+OpenPiton
Contributor: Seongwon Jo
This project aims to bring Ariane+OpenPiton closer to RISC-V RVA23 compliance by adding support for the Svadu extension. By enabling hardware-managed...
RISC-V
Generate Counter Examples for Bounded Model Checks in CIRCT
Contributor: Shri Vishakh Devanand
circt-bmc can already prove when an assertion is falsifiable, but it does not yet produce the counterexample trace format hardware developers rely on...
Generic MinimumLinuxBoot for RTL Simulations
Contributor: Xuhai Chang
Booting Linux in OpenPiton's Verilator RTL simulation takes days. This project builds a checkpoint/restore pipeline: boot Linux in QEMU (minutes),...
PeakRDL Exporter Plugin for CSR Visualization on Makerchip
Contributor: Ali Mohsen
The project aims to add an exporter plugin for PeakRDL that enables a high level visualization for control & status register (CSR) design using...
verilog
Device-Under-Test Python Typing Stub Generator for cocotb tests
Contributor: chaitanyasharma
This project aims to create a tool that automatically generates Python typing stubs for the Device Under Test (DUT) in cocotb-based hardware...
verilog
OpenRISC Linux Feature Development
Contributor: Chen Miao
Jump Label Implementation aims to eliminate branch overhead in kernel code by dynamically patching JMP/NOP instructions at runtime using GCC's...
Compiler
Architectural Improvements to OpenPiton+Ariane for RISC-V Profile Compliance
Contributor: Jayishnu Uttane
This project aims to enhance the OpenPiton+Ariane architecture to progress toward RISC-V RVA23 profile compliance. The primary focus will be...
RISC-V
Metro-MPI++
Contributor: Kislay Arya
Modern RTL simulation is computationally expensive and often limited by single-node processing capabilities. This proposal aims to improve...
Transforming the OpenHW High Performance Data Cache into a High Performance Instruction Cache
Contributor: Akiho Kawada
Since CVA6/Ariane is highly modular by design, it is relatively easy to develop and integrate multiple L1 caches. Additionally, because CVA6/Ariane...
Implementing RISC-V Cache Management Operation Extensions in OpenPiton
Contributor: Suraj Shirvankar
The project aims to integrate RISC-V Cache Management Operation (CMO) extensions into the OpenPiton processor framework. This integration will...
RISC-V
Improving ATPG Fault Coverage in Fault
Contributor: Youssef Kandil
The semiconductor industry, driven by Moore's Law, continuously pushes the boundaries of integrated circuit (IC) technology, leading to...
TinyParrot: A minimal BlackParrot RISC-V Multicore variant
Contributor: Colin Knizek
TinyParrot is a BlackParrot RISC-V multi-core variant that aims to be small enough to fit onto educational FPGA development boards like the Pynq Z2....
RISC-V
Integration of Silicon Compiler Microservices into the TL-Verilog Mode in VS-Code
Contributor: Raj Aryan Singh
This project aims to enable the seamless integration of the Silicon Compiler's hardware design tools and flows within popular development...
Compilerverilog
Arcilator Vectorization
Contributor: Mohamed Atef
Add a vectorization support to Arcilator. An efficient vectorization pass will make Arcilator faster, as hardware designs often contain highly...
Circuit Visualization with Makerchip Platform
Contributor: Chaitravi Chalke
The Makerchip platform has added custom visualization support for circuit simulations, allowing for improved insights into microarchitectural...
Enhancing OpenPiton+Ariane SoC With an Open-Source Advanced Interrupt Architecture (AIA)
Contributor: Kinza Qamar Zaman
The Platform Level Interrupt Controller (PLIC) is the de facto interrupt controller in RISC-V systems. However, the specification has intrinsic...
RISC-V
Improving SDF support in Icarus Verilog
Contributor: Leo Moser
When you design a digital circuit, you want to make sure that all timings are correct, even post-layout. Therefore, the gate level netlist is...
verilog
Enhancing OpenPiton+Ariane With a High-Performance Data Cache
Contributor: Noelia Oliete Escuín
As the demand for High-Performance Computing (HPC) continues to grow, there is a need for open-source solutions that can deliver the performance...
RISC-V
Parameterized device layouts for GF180MCU
Contributor: Qurrat ul ain Alam
Throughout this project, I hope to gain a firmer understanding of TCL scripting and the backend working of parameterized devices and hopefully make...
Enhancing the Sootty Terminal-based Graphical Waveform Viewer
Contributor: Yihua Liu
Sootty is a novel graphical waveform viewer targeted at modern terminals, however, it currently only supports VCD format and decimal system, not...
IRSIM Dynamic Power Analysis and Other Improvements
Contributor: Jason Liang
Large digital designs are prone to consume lots of power and thus, a tool for power analysis is needed. There are two types of power analyses:...
verilog
Improving Query Language Features in Sootty
Contributor: L Lakshmanan
My proposal aims to make Sootty, a CLI waveform viewer, a more utilitarian and intuitive tool to use, by adding features that I believe it would...
Development Framework for Open MPW Shuttles
Contributor: Ali Imran
Efabless, Google, and SkyWater Technologies, through the Open MPW and ChipIgnite programs, provide free ASIC fabrication. To help streamline the...
verilog
Logical Equivalence Checks with CIRCT
Contributor: Dragoș Cristian Lizan
The CIRCT project is an open-source effort to develop Circuit Intermediate Representations, Compilers, and Tools by applying the MLIR and LLVM...
Compiler
Enhancing AnyCore, a superscalar RISC-V processor
Contributor: Gergely Bálint
AnyCore is an advanced superscalar processor developed at NC State University, designed to be highly configurable across parameters like issue width...
RISC-V
1st CLaaS for PYNQ FPGAs
Contributor: Shrihari
Utilizing cloud FPGAs prove to be very expensive and minor coding bugs could consume precious compute cycles and incur hefty bills. This proves using...
verilog
TinyParrot: A minimal BlackParrot RISC-V Multicore variant
Contributor: Kinza Qamar Zaman
This project aims to shrink BlackParrot multicore to have a minimal variant called TinyParrot multicore. The main goal of this project is to get very...
RISC-V
Parallelising Verilog RTL Simulations Using MPI
Contributor: Guillem Lopez Paradis
This project will focus on a current problem in the Hardware community: The speed of RTL Simulations. These types of simulations are a necessary step...
verilog
M-extension support for SERV
Contributor: Zeeshan Rafique
This project aims to design and integrate the integer “Multiplication and Division Unit (MDU)” with SERV core as a co-processor. The MDU will support...
RISC-V
Bring up CV32E40P AI accelerator on FPGA
Contributor: Veronia Iskandar
The open-source RISC-V instruction set architecture is gaining interest throughout industry and academia. One advantage of RISC-V is the ability to...
RISC-V
Formal Verification of Mor1kx processor using Yosys-Formal tools
Contributor: Harshitha S
OpenRISC’s mor1kx is one of the old open source projects with more sophisticated and multi-core features. FuseSoC support for mor1kx makes it unique,...
verilog
WARP-V Many-Core in the Cloud
Contributor: Vineet Jain
The WARP-V is an open-source and highly configurable, adaptable, and flexible Core generator. It supports various ISA like MIPS, Open-Source RISC-V,...
RISC-VverilogWeb
Black Parrot on Open-Source Google-Skywater 130nm node
Contributor: Lakshmi S
Black Parrot is a tiny, modular Linux capable open-source processor core that encourages external contributions and strives for infrastructure...
Block Based Circuit Design
Contributor: Ninad Jangle
Block-Based Circuit Design is a solution to counter the complexity of Circuit Design. We aim to develop and deploy a Block-Based TL-Verilog solution...
verilog
Virtual FPGA Lab
Contributor: Bala Dhinesh
Field-Programmable Gate Array(FPGA) is a hardware circuit that a user can program to carry out logical operations. FPGAs are beneficial for...
Porting BaseJump STL to FuseSoC
Contributor: Adithya Sunil Edakkadan
The objective of this project is to port BaseJump STL to FuseSoC so that new projects can directly reuse these hand-optimized IP cores rather than...
verilog
Multi-level TLB support for Ariane
Contributor: Nazerke Turtayeva
The memory to CPU bottleneck is one of the fundamental and essential issues of commodity processors. With sweeply increasing computing speed,...
RISC-V
TensorCore Extension for Deep Learning
Contributor: Nitin Mishra
Deep Learning continues to be a key application for a range of services nowadays - from autonomous vehicles to data centers and even in embedded...
RISC-V
AUTOMATING HARDWARE AND BITSTREAM VERIFICATION FOR PRGA WITH COCOTB
Contributor: Ansh Puvvada
The goal of the project is to automate and augment the verification of the custom FPGA and the bitstream with Cocotb, an open-source framework for...
verilogvhdl
Integrating ao486 with BYOC Framework
Contributor: Manan Gupta
This project involves a heterogeneous-ISA system based on a BYOC (Bring Your Own Core) framework. This provides a cache coherent, manycore research...
Integration of WARP-V with OpenPiton
Contributor: Shivam Potdar
WARP-V is an open-source and highly flexible and configurable CPU core with customisable ISA and pipelines written in the emerging...
RISC-Vverilog
Enhancement in Warp-V and Optimization
Contributor: VineetJain07
The WARP-V RISC-V core generator was developed in 2018, it is the most-configurable, most-adaptable open-source RISC-V CPU core generator, taking...
RISC-Vverilog
Extend Librecores.org in terms of User Interactivity and Feedback
Contributor: Aquib Baig
This project aims to develop user interactivity on the website through a full-fledged notification system and a platform to record user feedback. The...
Web
Microarchitectural enhancement of Ariane
Contributor: Zach Zheng
This project is to add Microarchitectural enhancement of Ariane that is a popular open-source CPU core implementing the RISC-V ISA (instruction set...
RISC-V
Analysis of WARP-V on FireSim with RocketChip
Contributor: Alaa Salman
Analysis of the architectural performance of WARP-V using FireSim and RocketChip Chisel code. Adding WARP-V to RocketChip to utilize the capabilities...
FPGA-Accelerated Web Applications
Contributor: Ákos Hadnagy
Building hardware requires access to costly tools and hardware, furthermore complexity in hardware design remains a deterrent force. FPGAs in the...
Web
Enhancing JuxtaPiton with X86 Support
Contributor: Kunal Gulati
JuxtaPiton is an architecture being developed at Princeton’s Parallel Group for heterogeneous ISA research. For this project, I will replace the...
Continuous Integration for Hardware Projects on LibreCores CI
Contributor: Nancy Chauhan
Librecores provides a platform to share projects and ideas, in the area of free and open source digital hardware design. Librecores CI is an...
LLVM Code Generation for RISC-V Open Source GPU
Contributor: Reshabh Sharma
Bespoke Silicon group at University of Washington is working on the second version of their open source RISC-V manycore processor. They are also...
RISC-V
Develop a Transaction-Level Verilog Component Library
Contributor: Ahmed Salman
Transaction-Level Verilog (TL-Verilog) is an emerging language extension to System Verilog, Has the ability to define flexible reusable components. ...
verilog
Digital Filter Block Implementations in MyHDL and PyFDA Integration
Contributor: Sriyash Caculo
Design and implementation of digital filters is essential for electronics engineers. Digital filter design in hardware usually is a two stage...
verilogvhdl
Improve the LibreCores.org in terms of discoverability
Contributor: Sandip Kumar Bhuyan
LibreCores.org lists free and open source “IP Cores” on the website for the community to view and use. All listed projects are backed by a git...
Web
Formal verification of WARP-V processor
Contributor: Ákos Hadnagy
WARP-V is an emerging open-source CPU core generator for RISC-V CPUs. It benefits from the flexibility of Transaction-Level Verilog (TL-Verilog) to...
RISC-Vverilog
BaseJump STL Hacker
Contributor: kunalgulati
I'm proposing the creation of a Math Library for BaseJump STL. Adding a set of routines that employ the CORDIC algorithm to implement directly and...
Enable DEVSIM to simulate solar cells
Contributor: Noe Nieto
DEVSIM is a TCAD (Technology Computer Aided Design) semiconductor device simulation software. TCAD tools are special simulation software that can...
Integration of OpenRISC Linux Port into OpTiMSoC
Contributor: Pedro Henrique Penna
Open Tiled Manycore System-on-Chip (OpTiMSoC) is an open-source framework that allows one to design and prototype manycore-based platforms on FPGA...
EDSAC Museum on FPGA
Contributor: hatim
Electronic Delay Storage Automatic Calculator (EDSAC) is a first generation British computer commissioned in 1949. It was built by Maurice Wilkes and...
verilog
Quality metrics for projects listed on LibreCores.org
Contributor: Amitosh Swain Mahapatra
LibreCores.org lists free and open source "IP Cores" on the website for the community to view and use. Currently the website extracts the project...
Web
Updating Sodor
Contributor: kritik bhimani
Update riscv-sodor currently implemented in Chisel2 to Chisel3 along with that also update Privilege ISA Spec it complies to from 1.7 to 1.10 and...
QEMU port of OpenRISC
Contributor: Dalmon Ian
QEMU is a free and open virtual machine software that can be useful for the OpenRISC community for testing and teaching software development on the...
Yosys Tools: Automatic schematic generation for web browsers
Contributor: Rishabh Rawat
Schematics are a great way to understand electronic circuits, and specially when we are using high level descriptions, it becomes essential that we...
verilogWeb
RISC-V port to Parallela
Contributor: eliaskousk
With this proposal I hope to benefit the open-source hardware enthusiast community with work related to the incredible Parallela board used by...
RISC-V